features 2.5v and 3.3v power supply options guaranteed ac parameters over temperature: ? max > 3.0ghz < 35ps within-device skew < 350ps t r /t f < 490ps propagation delay (differential) wide temperature range: ?0 c to +85 c differential design v bb output fully compatible with industry standard 100k i/o levels available in 32-pin tqfp package the SY100EP210U is a high-speed, precision low skew 1-to-5 dual differential clock driver. hstl inputs can be used when the ep210u is operating in pecl mode. the ep210u specifically guarantees critical ac parameters over temperature and voltage. optimal design, layout, and processing minimize skew within device and from device-to-device. the SY100EP210U, as with most other ecl devices, can be operated from a positive v cc supply in pecl mode. this allows the ep210u to be used for high performance clock distribution in +3.3v or +2.5v systems. single-ended input operation is limited to a v cc 3.0v in pecl mode, or v ee ?.0v in ecl mode. designers can take advantage of the ep210u? performance to distribute low skew clocks across the backplane or to multiple points on a board. 2.5v/3.3v dual 1:5 differential lvecl/lvpecl/hstl clock driver description clockworks SY100EP210U final 1 rev.: a amendment: /2 issue date: august 2001 block diagram qa0 /qa0 qa1 /qa1 qa2 /qa2 qa3 /qa3 qa4 /qa4 clka /clka qb0 /qb0 qb1 /qb1 qb2 /qb2 qb3 /qb3 qb4 /qb4 clkb /clkb v bb 75k ? 75k ? v ee v ee v cc 75k ? v ee 75k ? 75k ? v cc v ee 75k ?
2 clockworks SY100EP210U micrel pin configuration 32 31 30 29 28 27 26 25 9 10111213141516 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 vcc nc clka /clka vbb clkb /clkb vee qa3 /qa3 qa4 /qa4 qb0 /qb0 qb1 /qb1 vcc qa0 /qa0 qa1 /qa1 qa2 /qa2 vcc vcc /qb4 qb4 /qb3 qb3 /qb2 top view tqfp t32-1 qb2 vcc pin function clka, /clka lvpecl, lvecl, hstl clock input: clka input includes a 75k ? pull-down. default is low if left floating. /clka includes both pull-up and pull-down resistors. default condition is v cc /2. clkb, /clkb lvpecl, lvecl, hstl clock input: clkb input includes a 75k ? pull-down. default is low if left floating. /clkb includes both pull-up and pull-down resistors. default condition is v cc /2. qn0:4, /qn0:4 lvpecl or lvecl outputs: terminate to v cc 2v. (see termination section) v bb reference voltage for single-ended inputs: it provides the switching reference for the input differential amplifier. when used, bypass with a 0.0 f capacitor to the most positive reference (usually v cc ) as shown in figure 3. v cc positive power supply: for lvpecl operation, connect v cc to 3.3v or 2.5v. for lvecl operation, connect to gnd. bypass with 0.1 f//0.01 f low esr capacitors. v ee negative power supply: for lvpecl operation, connect to gnd. for lvecl operation, connect to 3.3v or 2.5v. pin names symbol rating value unit v cc v ee power supply voltage 6.0 v v in input voltage (v cc = 0v, v in not more negative than v ee ) 6.0 to 0 v input voltage (v ee = 0v, v in not more positive than v cc ) +6.0 to 0 v i out output current continuous 50 ma surge 100 i bb v bb sink/source current (2) 0.5 to 0 ma t a operating temperature range 40 to +85 c t store storage temperature range 65 to +150 c ja package thermal resistance still-air 50 c/w (junction-to-ambient) 500lfpm 42 jc package thermal resistance 20 c/w (junction-to-case) absolute maximum ratings (1) notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional oper ation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum r atlng conditions for extended periods may affect device reliability. 2. use for inputs of same package only.
3 clockworks SY100EP210U micrel t a = 40 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v cc power supply (lvpecl) 2.37 3.8 2.37 3.8 2.37 3.8 v voltage (lvecl) 2.37 3.8 2.37 3.8 2.37 3.8 i ee internal supply current 70 90 70 90 70 90 ma i ih input high current 150 150 150 av in =v ih i il input low current clka, clkb 0.5 0.5 0.5 av in =0v /clka, /clkb 150 150 150 av in =0v c in input capacitance 2 pf dc electrical characteristics (1) notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establ ished. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. t a = 40 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v ol output low voltage 555 680 895 555 680 895 555 680 895 mv 50 ? to v cc 2v v oh output high voltage 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv 50 ? to v cc 2v v ihcmr input high voltage (2) 1.2 v cc 1.2 v cc 1.2 v cc v common mode range 2.5v lvpecl dc electrical characteristics (1) v cc = 2.5v 10%, v ee = 0v notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establ ished. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. input and output v aries 1:1 with v cc . 2. the v ihcmr (min) varies with v ee . v ihcmr (max) varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. t a = 40 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v ih input high voltage 2135 2420 2135 2420 2135 2420 mv v il input low voltage 1490 1675 1490 1675 1490 1675 mv v ol output low voltage 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv 50 ? to v cc 2v v oh output high voltage 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv 50 ? to v cc 2v v bb output reference voltage (2) 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v ihcmr input high voltage 1.2 v cc 1.2 v cc 1.2 v cc mv common mode range (3) 3.3v lvpecl dc electrical characteristics (1) v cc = 3.3v 10% notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establ ished. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. input and output v aries 1:1 with v cc . 2. single-ended input operation is limited to v cc 3.0v in lvpecl mode. v bb reference varies 1:1 with v cc . 3. the v ihcmr (min) varies with v ee . v ihcmr (max) varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal.
4 clockworks SY100EP210U micrel t a = 40 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v il input low voltage 1810 1625 1810 1625 1810 1625 mv (single-ended) v ih input high voltage 1165 0880 1165 0880 1165 0880 mv (single-ended) v ol output low voltage 1945 1820 1695 1945 1820 1695 1945 1820 1695 mv 50 ? to v cc 2v v oh output high voltage 1145 1020 0895 1145 1020 0895 1145 1020 0895 mv 50 ? to v cc 2v v bb output reference voltage (2) 1525 1425 1325 1525 1425 1325 1525 1425 1325 mv v ihcmr input high voltage v ee +1.2 0.0 v ee +1.2 0.0 v ee +1.2 0.0 v common mode range (3) lvecl dc electrical characteristics (1) v ee = 2.375v to 3.8v; v cc = 0v notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establ ished. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. 2. single-ended input operation is limited to v ee 3.0v in ecl/lvecl mode. v bb reference varies 1:1 with v cc . 3. the v ihcmr (min) varies with v ee . the v ihcmr range is referenced to the most positive side of the differential input signal. t a = 40 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v ih input high voltage 1200 1200 1200 mv v il input low voltage 400 400 400 mv v x input crossover voltage 680 900 680 900 680 900 mv hstl dc electrical characteristics v cc = 2.375v to 3.8v; v ee = 0v
5 clockworks SY100EP210U micrel notes: 1. f max guaranteed for functionality only (toggel frequency). 2. clk 0 to bank a and clk 1 to bank b; differential. maximum propagation delay is worst-case, over temperature and voltage. 3. skew is measured between outputs under identical transitions. 4. measured for same transitions. 5. see timing waveform. t a = 40 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition f max maximum frequency (1) 3.0 3.0 3.0 ghz hstl/lvpecl t pd propagation delay (2) 220 300 380 270 350 430 300 410 490 ps t skew (3) within-device skew 20 25 20 25 20 25 ps part-to-part skew (4) 85 160 85 160 85 160 ps t jitter cycle-to-cycle jitter (rms) 0.2 < 1 0.2 < 1 0.2 < 1 ps(rms) v pp minimum input swing (5) 150 800 1200 150 800 1200 150 800 1200 mv t r , t r output rise/fall times 100 170 250 120 190 270 120 280 350 ps (20% to 80%) ac electrical characteristics (lvpecl) v cc = 2.375 to 3.8v, v ee = 0v; (lvecl) v ee = 2.375v to 3.8v, v cc = 0v timing waveform clka/b /clka/b 150mv to 1200mv product ordering code ordering package operating package code type range marking SY100EP210Uti t32-1 industrial xep210u SY100EP210Utitr* t32-1 industrial xep210u *tape and reel
6 clockworks SY100EP210U micrel typical characteristics 100 200 300 400 500 600 700 800 900 0 500 1000 1500 2000 2500 3000 3500 4000 output amplitude (mv) frequency (mhz) frequency response vs. out p ut am p litude v sup = 2.5v v diffin = 800mv frequency response vs. output amplitude @2.5v 100 200 300 400 500 600 700 800 900 0 500 1000 1500 2000 2500 3000 3500 4000 output amplitude (mv) frequency (mhz) frequency response vs. output amplitude v sup = 3.3v v diffin = 800mv frequency response vs. output amplitude @3.3v
7 clockworks SY100EP210U micrel termination recommendations r2 82 ? r2 82 ? z o = 50 ? z o = 50 ? +3.3v +3.3v v t = v cc 2v r1 130 ? r1 130 ? +3.3v figure 1. parallel termination thevenin equivalent notes: 1. for +2.5v systems: r1 = 250 ? r2 = 62.5 ? z = 50 ? z = 50 ? 50 ? 50 ? 46 ? to 50 ? +3.3v +3.3v source destination r b figure 2. three-resistor y termination notes: 1. power-saving alternative, thevenin termination. 2. place termination resistors as close to destination inputs as possible. 3. r b resistor sets the dc bias voltage, equal to v t . +3.3v +3.3v 50 ? z o = 50 ? 0.01 f v bb r2 82 ? +3.3v +3.3v r1 130 ? r1 130 ? r2 82 ? v t = v cc 2v q /q +3.3v figure 3. terminating unused i/o notes: 1. unused output (/q) must be terminated to balance the output. 2. micrel's differential i/o logic devices include a v bb reference pin . 3. connect unused input through 50 ? to v bb . bypass with a 0.01 f capacitor to gnd. 4. for +2.5v systems: r1 = 250 ? , r2 = 62.5 ?
8 clockworks SY100EP210U micrel micrel-synergy 3250 scott boulevard santa clara ca 95054 usa tel + 1 (408) 980-9191 fax + 1 (408) 914-7878 web http://www.micrel.com this information is believed to be accurate and reliable, however no responsibility is assumed by micrel for its use nor for an y infringement of patents or other rights of third parties resulting from its use. no license is granted by implication or otherwise under any patent or pat ent right of micrel inc. ? 2001 micrel incorporated 32 lead thin quad flatpack (t32-1) rev. 01
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